|
||
|
|||||||
| 瀏覽投票結果: [疑問]為什麼AMD XP不出512K L2 的CPU | |||
| 可能是AMD認為256K就可以打的P4死死的 |
  
|
43 | 15.03% |
| 可能是成本太高 |
  
|
30 | 10.49% |
| 可能是良率會太低 |
  
|
63 | 22.03% |
| 可能是架構還要修改 |
  
|
32 | 11.19% |
| 可能是留著當殺手ㄐ一ㄢˇ等0.13出來再用 |
  
|
51 | 17.83% |
| 可能是等K8再用 |
  
|
31 | 10.84% |
| 可能是會讓存貨難賣 |
|
7 | 2.45% |
| 可能是XP本身不支援 |
|
1 | 0.35% |
| 可能是效能增加不多 |
|
23 | 8.04% |
| 可能是????您覺得呢 |
|
5 | 1.75% |
| 投票者: 286. 您不可以參加此投票 | |||
|
|
|
主題工具 |
|
*停權中*
加入日期: Jan 2002
文章: 1,214
|
First I spelled "redundancy" wrong in my first reply so i apologize for any confusion that might cause.
see http://www.computer.org/proceedings...04060291abs.htm its a circuit/logic design technique to improve yield. Its not a process based tech. Also DRAM, EDRAM processes and logic processes are all different, and to achieve the clock speeds required by today's CPUs its impossible to use the EDRAM process provided by the various fabs. The main problem is transistor leakage. Also note that the 128MB L2 cache die used on Power4s are not based on the same processes the CPU core dies use. |
|||||||
2002-03-25, 05:30 AM
#31
|
|
|
*停權中*
加入日期: Jan 2002
文章: 1,214
|
引用:
thats assuming the cache latency/access time will increase with size, and/or your target application exhibit very low locality or already fit in the exisiting cache. The last case is clearly not true in K7's case. And since we have a process shrink to work with as well, the L2 cache may not be the critical path even if it doubled in size. 再來請問AMD的副總裁在那裡自己說的,我非常的想要有一個出處資料歐謝謝 引用:
maybe, maybe not. But since increasing the FSB speed offers much performance increase, increasing the L2 size likely will be beneficial. 引用:
that and marketing for K8 will be the main reason. 引用:
512KB and 1024KB versions will be aviliable. 引用:
Do you know exactly what you are talking about here? Or did you pass 微處理器基礎 as a fluke? 引用:
You really seem to lack a good understanding on how cache works. Especially hitrate/size, and under what condition L2 is helpful. 引用:
L2 size and hitrate's balance point would be a L2 the size of the whole addressing space provided by the architecture. Its hitrate, cost and access time one tries to balance. And on chip caches for a consumer chip are usually bound by the cost. |
|||||||||
|
2002-03-25, 06:19 AM
#32
|
|
|
*停權中*
加入日期: Jan 2002
文章: 171
|
再來請問AMD的副總裁在那裡自己說的,我非常的想要有一個出處資料歐謝謝
某期的pc diy 我明天去公司找一下 晚一點再根您說 |
|
2002-03-25, 09:50 AM
#33
|
|
|
*停權中*
加入日期: Jan 2002
文章: 171
|
查到了
十月份的PC 2000 161頁 自己看吧!!!!! 證明我沒亂講 |
|
2002-03-25, 08:43 PM
#34
|
|
|
Senior Member
 加入日期: Sep 2001
文章: 1,236
|
引用:
Can't open that PDF, need password and username.  And if PowerPC isn't used in same prcoess for core and cache, then I think more photo-masks will result in cost-increasing. Or they use another tech to package two die? Need your further comments, Thanks. |
|
|
2002-03-26, 01:53 AM
#35
|
|
|
*停權中*
加入日期: Jan 2002
文章: 1,214
|
引用:
Goto library, and learn how to access to these IEEE/ACM papers. 引用:
Note that Power and PowerPC are NOT the same line of processors. Power 4's L3 cache brief can be seem at http://www-1.ibm.com/servers/eserve...s/power4_4.html they mount the L3 data arraies on a MCM as the core chip. Examples of MCMs are pentium pro, mobile S3 savage4s, the new geforce 2 go. Also the main increased cost of using MCM is not the increased mask cost, but rather the yield. |
||
|
2002-03-26, 04:24 AM
#36
|
|
|
*停權中*
加入日期: Jan 2002
文章: 1,214
|
引用:
3Q3Q ........ 這種雜誌不好找..... |
|
|
2002-03-26, 04:28 AM
#37
|
|
|
Master Member
  加入日期: Apr 2001 您的住址: 台北縣三峽.中華
文章: 2,271
|
快取大小與效能的關係的問題
基礎的計算機結構就有講了 如果有讀過的人還搞錯要打屁屁....
__________________
PCDVD帶領著我,PCDVD教導著我,PCDVD保護著我,我因PCDVD的光輝繁榮茁壯,我因PCDVD的慈悲得到庇蔭,因PCDVD的智慧福順謙卑,我們活著只為了對PCDVD效忠,我的生命全屬於PCDVD......改編於巫師的第一守則 把機殼搞的像電子花車有啥意義......但是我也是....快跑  常出沒地帶.......PCDVD.......熊版 |
|
2002-03-26, 05:34 AM
#38
|
|
|
*停權中*
加入日期: Jan 2002
文章: 1,214
|
引用:
那可不可以請auroraice大大教導一下我們這些晚生後進這個問題的詳細解答呢? 高中是沒有教計算機結構的 |
|
|
2002-03-26, 09:36 AM
#39
|
|
|
Senior Member
加入日期: Sep 2001
文章: 1,236
|
Note that Power and PowerPC are NOT the same line of processors. Power 4's L3 cache brief can be seem at http://www-1.ibm.com/servers/eserve...s/power4_4.html they mount the L3 data arraies on a MCM as the core chip. Examples of MCMs are pentium pro, mobile S3 savage4s, the new geforce 2 go. Also the main increased cost of using MCM is not the increased mask cost, but rather the yield. [/QUOTE] MCM?  So they use this kind of package technology. I think the process-problem can be avoided by using this kind of package. But Intel or AMD use the same package to combine core and cache? If they don't, then they still have to face the process problem to deal with logic and memory at same time. Maybe the redudancy-protect tech. can help some, I still have no not read it carefully. Is it popular in 業界 now? |
|
2002-03-26, 06:16 PM
#40
|
|
