EE Design has a interesting article on the Geforce4 Ti chip.

63 million transistors, 78% logic

50% of RTL from GF3 modified

400k lines C , 800k lines Verilog

Schedule targets: 9 months (!!) to tapeout, 100 days from tapeout to ramp

40 to 70 engineers in implementation alone

$160 million in tools, $40 million of which on emulation

http://www.eedesign.com/story/OEG20020612S0051