引用:
Originally posted by idiot
you seem to have a huge misunderstanding in that peopleuse DRAMs for cache. People use SRAM in most cases, and there are no manufacturing problems associated with it.
Most of the high performance MPUs you can get your hands on have redanduncy protections in their cache arrays.
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Sorry, I used the wrong usage.
But in my previous knowledge, DRAM and SRAM are both in memory category. And I heard from a teacher in on-job training:
For memory, they have to make the capactior cell as good as they can, but for logic, they have to shrink the length as possible as they can.
And I think they are very different in process, that's why I wonder how good the yield rate they can achieve if they want to produce core-logic with embeded memory in one die (not by MCM package). That's why I asked if there're some design-skills which can avoid or improve that?
Or they just conquer the process problem?
(Sorry, I left process field for 3 years, not familiar with it anymore)