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文章: 193
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Originally posted by idiot
thats assuming the cache latency/access time will increase with size, and/or your target application exhibit very low locality or already fit in the exisiting cache. The last case is clearly not true in K7's case. And since we have a process shrink to work with as well, the L2 cache may not be the critical path even if it doubled in size.
再來請問AMD的副總裁在那裡自己說的,我非常的想要有一個出處資料歐謝謝
maybe, maybe not. But since increasing the FSB speed offers much performance increase, increasing the L2 size likely will be beneficial.
that and marketing for K8 will be the main reason.
512KB and 1024KB versions will be aviliable.
Do you know exactly what you are talking about here? Or did you pass 微處理器基礎 as a fluke?
You really seem to lack a good understanding on how cache works. Especially hitrate/size, and under what condition L2 is helpful.
L2 size and hitrate's balance point would be a L2 the size of the whole addressing space provided by the architecture. Its hitrate, cost and access time one tries to balance. And on chip caches for a consumer chip are usually bound by the cost.
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其實同樣的道理應用在L1 chahe上也是大同小異的,舉個例子來講,Cyrix的6x86CPU
(後來改稱MII)為了增加效能而將L1 chahe加大到64K,但實際運作起來其整數效能還不及僅有16K L1 chahe的Pentium with MMX(至於AMD K6就更不用講了). |