引用:
Originally posted by Aloof
MCM? 
So they use this kind of package technology.
I think the process-problem can be avoided by using this kind of package.
But Intel or AMD use the same package to combine core and cache?
If they don't, then they still have to face the process problem to deal with logic and memory at same time.
Maybe the redudancy-protect tech. can help some, I still have no not read it carefully. Is it popular in 業界 now?
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you seem to have a huge misunderstanding in that peopleuse DRAMs for cache. People use
SRAM in most cases, and there are no manufacturing problems associated with it.
Most of the high performance MPUs you can get your hands on have redanduncy protections in their cache arrays.
auroraice大大: 您還沒解釋快取大小與效能的關係的問題呢.