引用:
Originally posted by ewingshih
引述:
快取的大小必須看設計的需求,有時大不一定會使效能快很多.....
這個有學過微處理器基礎的朋友應該都學過這個吧
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
這才是標準答案
AMD的副總裁自己說的
|
thats assuming the cache latency/access time will increase with size, and/or your target application exhibit very low locality or already fit in the exisiting cache. The last case is clearly not true in K7's case. And since we have a process shrink to work with as well, the L2 cache may not be the critical path even if it doubled in size.
再來請問AMD的副總裁在那裡自己說的,我非常的想要有一個出處資料歐謝謝
引用:
並不是不願意生產512K
實在是沒必要
因為以目前的K-7設計架構來說
加到512K效能並不會帶來多大的提升
|
maybe, maybe not. But since increasing the FSB speed offers much performance increase, increasing the L2 size likely will be beneficial.
引用:
再加上生產上的良率及成本考量
所以不考慮生產512K的K-7
|
that and marketing for K8 will be the main reason.
引用:
但k-8是個全新架構的產品
可能會使用512K甚至更大
|
512KB and 1024KB versions will be aviliable.
引用:
至於p-4因為管線設計的太深了
所以必需加大L2
才能充份發揮20條管線的工作效率
|
Do you know exactly what you are talking about here? Or did you pass 微處理器基礎 as a fluke?
引用:
一昧加大快取
但命中率太低的話
所有的資料還是要再回存至L1
到時L1被塞爆
只會讓整體的效能往下降
|
You really seem to lack a good understanding on how cache works. Especially hitrate/size, and under what condition L2 is helpful.
引用:
所以要取L2的大小和命中率之間的平橫點
才是cpu設計的一門大學問
一般人不要太誤信L2大就是王道
這是錯誤的觀念
|
L2 size and hitrate's balance point would be a L2 the size of the whole addressing space provided by the architecture. Its hitrate, cost and access time one tries to balance. And on chip caches for a consumer chip are usually bound by the cost.