雲姬: WCPUID's info on L2 latency is utterly BS, the current XP cores and TB have a L1 miss + L2 hit latency of either 11 or 19/20 depends on if the victim cache is full? (victim cache is 8 entries deep)

And Cumine's L1 miss L2 hit latency is 7 cycles (3+4), while P4's is about 9 to 18 cycles or 8 to 16 cycles (NW).


Cache also does not using that much power, Cumine's L2 uses about 3.4W max per Intel's conference paper.

And yes i would agree that a 256bit or even 512bit L1/L2 path would benefit K7s and 512KB L2 is a good step up as well.

A widened path in K7's case would provide lower effective latency in the real world.